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Omit boards, wires, traces, terminals, etc from Spice netlist output

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Branislav Stojkovic
2025-03-17 16:08:02 +01:00
parent 521301d7ef
commit f06bd0d49c
2 changed files with 11 additions and 2 deletions
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diylc/diylc-core/src/main/resources/update.xml
+4
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@@ -265,6 +265,10 @@
<changeType>IMPROVEMENT</changeType>
<description>Improved robustness of series/parallel graph construction code used in circuit analysis</description>
</org.diylc.appframework.update.Change>
<org.diylc.appframework.update.Change>
<changeType>IMPROVEMENT</changeType>
<description>Omit boards, wires, traces, terminals, etc from Spice netlist output</description>
</org.diylc.appframework.update.Change>
<org.diylc.appframework.update.Change>
<changeType>BUG_FIX</changeType>
<description>Moving selected components with a mouse doesn't register file modification action and doesn't enable Undo action</description>