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https://github.com/bancika/diy-layout-creator
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Omit boards, wires, traces, terminals, etc from Spice netlist output
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@@ -265,6 +265,10 @@
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<changeType>IMPROVEMENT</changeType>
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<changeType>IMPROVEMENT</changeType>
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<description>Improved robustness of series/parallel graph construction code used in circuit analysis</description>
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<description>Improved robustness of series/parallel graph construction code used in circuit analysis</description>
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</org.diylc.appframework.update.Change>
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</org.diylc.appframework.update.Change>
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<org.diylc.appframework.update.Change>
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<changeType>IMPROVEMENT</changeType>
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<description>Omit boards, wires, traces, terminals, etc from Spice netlist output</description>
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</org.diylc.appframework.update.Change>
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<org.diylc.appframework.update.Change>
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<org.diylc.appframework.update.Change>
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<changeType>BUG_FIX</changeType>
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<changeType>BUG_FIX</changeType>
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<description>Moving selected components with a mouse doesn't register file modification action and doesn't enable Undo action</description>
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<description>Moving selected components with a mouse doesn't register file modification action and doesn't enable Undo action</description>
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@@ -61,9 +61,14 @@ public class SpiceAnalyzer extends NetlistAnalyzer implements INetlistAnalyzer {
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protected Summary summarize(Netlist netlist, Node preferredOutput) throws TreeException {
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protected Summary summarize(Netlist netlist, Node preferredOutput) throws TreeException {
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// grab all components that are in the netlist
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// grab all components that are in the netlist
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List<IDIYComponent<?>> allComponents = netlist.getComponents();
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List<Group> groups = netlist.getSortedGroups();
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List<Group> groups = netlist.getSortedGroups();
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List<IDIYComponent<?>> allComponents = groups.stream()
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.flatMap(x -> x.getNodes().stream()
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.map(y -> y.getComponent()))
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.distinct()
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.collect(Collectors.toList());
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int unconnectedIndex = groups.size();
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int unconnectedIndex = groups.size();
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int maxLen = 0;
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int maxLen = 0;
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